1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of testing a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit which can be burn-in-tested even when packaged and a method of burn-in-testing a semiconductor integrated circuit even when the semiconductor integrated circuit is packaged.
2. Description of the Related Art
In general, it takes a considerable amount of time to test the lifetime of semiconductor memory devices in an actual operating environment. Thus, it is necessary to reduce the test time while providing precise test results. To meet this necessity, burn-in tests are widely used.
In burn-in tests, products are tested under poorer conditions than in an actual operating environment by applying excessive stress within a short period of time. Memory vendors sell products that have passed such burn-in tests, and can thus guarantee predetermined lifetime when driven in an actual operating environment.
In order to enhance the efficiency of burn-in tests, a wafer burn-in test method has been adopted. The wafer burn-in test method involves performing tests in read and write operations, as well as performing direct current (DC) tests, to efficiently screen out defective chips. Such chips may include devices such as memory devices, that are to be tested.
FIG. 1 is a block diagram of a conventional wafer burn-in apparatus. Referring to FIG. 1, a plurality of chips on a wafer are divided into a plurality of dies by scribe lines (not shown), and each of the chips includes a wafer burn-in test circuit 10 and a plurality of dummy pads 20 for applying various power supply voltages needed for a burn-in test, and also includes the semiconductor devices to be tested.
The wafer burn-in test circuit 10 receives a signal WBE and generates a test master signal. In order to stably provide direct current (DC) power supply voltages required for a burn-in test, power supply voltages VPP, VBB, VBL, and VP are input from one or more sources external to the wafer burn-in apparatus via the dummy pads 20. In addition, the wafer burn-in test circuit 10 receives an address signal via an address pad (not shown) and performs a burn-in operation compatible with each test mode.
However, once the chip is packaged, the dummy pads 20 cannot be connected to an external device, and thus, the wafer burn-in test circuit 10 cannot be burn-in-tested. Therefore, research has been vigorously conducted to develop semiconductor integrated chips which can be burn-in-tested even after packaged. U.S. Pat. No. 5,471,429 discloses semiconductor devices which can be burn-in-tested even when packaged.
In the case of burn-in-testing input/output (I/O) circuits inside a semiconductor integrated circuit after packaging the semiconductor integrated circuit, a burn-in test apparatus may consume a considerable amount of current. For example, the current consumption of a delay locked loop (DLL), which is a type of I/O circuit that can be included in a semiconductor integrated circuit, may considerably increase when the DLL operates in a test mode. In a static burn-in test, nodes of a DLL are respectively fixed either to a power supply voltage or to a ground voltage, and thus, static stress may not be uniformly applied to all elements of a semiconductor integrated circuit.
FIG. 2 is a circuit diagram of an I/O circuit 200 comprising a plurality of nodes N1 through Nm. Referring to FIG. 2, in the I/O circuit 200, a plurality of first through m-th inverters, designated as I1 through Im, are connected in series. If an operation signal OPS having a logic high level is applied to the I/O circuit 200 when the I/O circuit 200 is burn-in-tested, the first node N1 is fixed to a low voltage level, the second node is fixed to a high voltage level, and the third node N3 is fixed to the low voltage level and so on. The m-th node Nm is fixed either to the high voltage level or to the low voltage level, depending on the level of its input.
Each of the inverters I1 through Im comprises a Positive Metal-Oxide Semiconductor (PMOS) transistor and a Negative Metal-Oxide Semiconductor (NMOS) transistor that are connected in series. When the first node N1 is fixed to the low voltage level during a burn-in test, the PMOS transistor of the second inverter I2 is turned on so that stress can be applied to that PMOS transistor. But the NMOS transistor of the second inverter I2 is turned off so that stress cannot be applied to the NMOS transistor. In the same manner, stress is applied to either the PMOS transistor or the NMOS transistor in each of the inverters I1 through Im, according to the voltage of the corresponding node. Therefore, in a static burn-in test mode, all elements of a packaged semiconductor integrated circuit may not be properly tested.